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dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
1/38 preliminary ? semiconductor ml9090-01,-02 lcd driver with key scanner and ram general description the ml9090-01 and ml9090-02 are lcd drivers that contain internal ram and a key scan function. they are best suited for car audio displays. since 1-bit data of the display ram corresponds to the light-on or light-off of 1-dot of the lcd panel (a bit map system), a flexible display is possible. a single chip can implement a graphic display system of a maximum of 80 16 dots (80 8 dots for the ml9090-01, 80 16 dots for the ml9090-02) and an arbitrator display system of 80 2 dots. since containing voltage multipliers, the ml9090-01 and ml9090-02 require no power supply circuit to drive the lcd. since the internal 5 5 scan circuit has eliminated the needs of key scanning by the cpu, the ports of the cpu can be efficiently used. features ? logic voltage: v dd 2.7 to 5.5 v ? lcd drive voltage: v bi 6 to 16 v (positive voltage) ? 80 segment outputs,10 common outputs for ml9090-01 and 18 common outputs for ml9090- 02 ? built-in bit-mapped ram (ml9090-01: 80 10 = 800 bits, ml9090-02: 80 18 = 1440 bits) ? 4-pin serial interface with cpu: cs , cp , di/o, kreq ? built-in lcd drive bias resistors ? built-in voltage doubler and tripler circuits ? built-in 5 5 key scanner ? port a output : 1 pin, output current: -15ma: (may be used for led driving) ? port b output : 8 pins output current (available for the ml9090-01 only) C2ma : 5 pins C15ma : 3 pins ? temperature range: C40 to +85?c ? package: 128-pin plastic qfp (qfp128-p-1420-0.50-k) (product name: ML9090-01GA) (product name: ml9090-02ga) model ml9090-01 ml9090-02 display duty 1/8 1/9 1/10 1/16 1/17 1/18 no. of display lines 8 9 10 16 17 18 no. of port b outputs 8 8 8 application ? car audio pedl9090-02 this version: jan. 2000 previous version: nov. 1998
? semiconductor ml9090-01,-02 2/38 pedl9090-02 block diagram ml9090-01 co c1 c2 c3 c4 r0 r1 r2 r3 pa0 r4 kreq y address counter y address decoder line address decoder y address regiser input output interface display line counter display data ram 80 10 bits data latch 80-out segment driver voltage doubler/ tripler lcd bias voltage dividing circuit x address decoder 8-port driver 10-out common driver shift register timing generator x address counter x address register i/o buffer com1 v in v 2 v 3b v 3a cs osc1 reset cp osc2 test di/o v dd v ss v c1 v c2 v s1 v s2 dt pb0 seg1 com10 pb7 seg80 oscillation circuit 1 port driver 5 5 key scanner control register
? semiconductor ml9090-01,-02 3/38 pedl9090-02 block diagram ml9090-02 y address counter y address decoder line address decoder y address regiser display data ram 80 18 bits data latch shift register 80-out segment driver x address decoder 18-out common driver timing generator x address counter x address register i/o buffer com1 seg1 com18 seg80 co c1 c2 c3 c4 r0 r1 r2 r3 pa0 r4 kreq input output interface display line counter voltage doubler/ tripler lcd bias voltage dividing circuit v in v 2 v 3b v 3a cs osc1 reset cp osc2 test di/o v dd v ss v c1 v c2 v s1 v s2 dt oscillation circuit 1 port driver 5 5 key scanner control register
? semiconductor ml9090-01,-02 4/38 pedl9090-02 pin configuration (top view) ml9090-01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 seg73 seg72 seg69 seg68 seg67 seg66 seg65 seg64 seg63 seg62 seg61 seg60 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 seg47 seg46 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 seg35 seg34 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg74 seg75 seg76 seg77 seg78 seg79 seg80 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 pb0 pb1 pb2 pb3 pb4 pb7 pa0 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 v dd osc2 osc1 dt v 2 v 3b v 3a v in v c1 v c2 v s1 v s2 v ss test reset kreq di/o cs cp c0 c1 c2 c3 c4 r0 r1 r2 r3 r4 seg1 seg2 seg3 seg4 seg5 seg8 seg9 128-pin plastic qfp seg71 seg70 seg33 seg32 seg6 seg7 pb5 pb6
? semiconductor ml9090-01,-02 5/38 pedl9090-02 pin configuration (top view) ml9090-02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 seg73 seg72 seg69 seg68 seg67 seg66 seg65 seg64 seg63 seg62 seg61 seg60 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 seg47 seg46 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 seg35 seg34 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg74 seg75 seg76 seg77 seg78 seg79 seg80 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com18 pa0 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 v dd osc2 osc1 dt v 2 v 3b v 3a v in v c1 v c2 v s1 v s2 v ss test reset kreq di/o cs cp c0 c1 c2 c3 c4 r0 r1 r2 r3 r4 seg1 seg2 seg3 seg4 seg5 seg8 seg9 128-pin plastic qfp seg71 seg70 seg33 seg32 seg6 seg7 com16 com17
? semiconductor ml9090-01,-02 6/38 pedl9090-02 absolute maximum ratings parameter power supply voltage symbol v dd condition ta = 25c rating C0.3 to +7.0 unit v applicable pins v dd bias voltage v bi ta = 25c C0.3 to +18.0 v v c1 , v c2 , v s1 , v s2 , v 2 , v 3a , v 3b voltage multiplier reference voltage v in ta = 25c C0.3 to +9.84 vv in ta = 25c *1 *2 C0.3 to +7.36 input voltage v i ta = 25c C0.3 to v dd +0.3 v cs , cp , di/o, osc1, reset , dt, test, c0 to c4 output current i o ta = 25c C20 ma pa0, pb5 to pb7 ta = 25c C3 ma pb0 to pb4 power dissipation p d ta = 85c 190 mw storage temperature t stg C55 to +150 ?c *1: when ta = 25?c and the voltage doubler is used, use voltage multiplier reference voltage v in values within a range that does not exceed the maximum bias voltage. *2: when ta = 25?c and the voltage tripler is used, use voltage multiplier reference voltage v in values within a range that does not exceed the maximum bias voltage. recommended operating conditions parameter power supply voltage symbol v dd condition range 2.7 to 5.5 unit v applicable pins v dd bias voltage v bi *1 6.0 to 16.0 v v s2 voltage multiplier reference voltage v in *2 3.0 to 8.8 vv in *3 2.0 to 6.6 operating frequency f op r = 56k w 2% 480 to 1200 khz osc1 operating temperature t op C40 to +85 ?c *1: for the bias voltage, v s2 is the maximum voltage potential and v ss is the minimum voltage potential. v s2 > v 2 3 v 3a , v 3b > v ss . *2: when the voltage doubler is used, use voltage multiplier reference voltage v in values within a range that does not exceed the maximum bias voltage. *3: when the voltage tripler is used, use voltage multiplier reference voltage v in values within a range that does not exceed the maximum bias voltage.
? semiconductor ml9090-01,-02 7/38 pedl9090-02 electrical characteristics dc characteristics parameter "h" input voltage 1 symbol v ih1 condition min. 0.85v dd typ. max. v dd unit v applicable pins osc1 "h" input voltage 2 v ih2 0.85v dd v dd v reset "h" input voltage 3 v ih3 0.85v dd v dd v cp "h" input voltage 4 v ih4 0.8v dd v dd v cs , di/o, c0 to c4 "l" input voltage 1 v il1 0 0.15v dd v osc1 "l" input voltage 2 v il2 0 0.15v dd v reset "l" input voltage 3 v il3 0 0.15v dd v cp "l" input voltage 4 v il4 0 0.2v dd v cs , di/o, c0 to c4 hysteresis voltage 1 v his1 v dd = 5 v 0.3 v osc1 hysteresis voltage 2 v his2 v dd = 5 v 0.4 v cp hysteresis voltage 3 v his3 v dd = 5 v 0.4 v reset "h" input current 1 i ih1 v i = v dd 10 m a reset "h" input current 2 i ih2 v i = v dd 10 m a c0 to c4 "h" input current 3 i ih3 v i = v dd 10 m a di/o "h" input current 4 i ih4 v i = v dd 1 m a osc1, cs , cp , dt, test "l" input current 1 i il1 v dd = 5 v, v i = 0 v C0.02 C0.05 C0.1 ma reset "l" input current 2 i il2 v dd = 5 v, v i = 0 v C0.18 C0.45 C0.9 ma c0 to c4 "l" input current 3 i il3 v i = 0 v v dd C0.4 C10 m a di/o "l" input current 4 i il4 v i = 0 v 0.9v dd C1 m a osc1, cs , cp , dt, test "h" output voltage 1 v oh1 i o = C0.4ma v dd C1.7 v di/o, kreq "h" output voltage 2 v oh2 i o = C40 m a v dd C1.2 v osc2 "h" output voltage 3 v oh3 i o = C15ma v dd C2.0 v pa0, pb5 to pb7 "h" output voltage 4 v oh4 i o = C2ma v pb0 to pb4 "h" output voltage 5 v oh5 i o = C50 m av r0 to r4 "l" output voltage 1 v ol1 i o = 0.4ma 0.4 v di/o, kreq "l" output voltage 2 v ol2 i o = 40 m a 0.1v dd v osc2 "l" output voltage 3 v ol3 i o = 1ma 0.4 v pa0, pb0 to pb7 "l" output voltage 4 v ol4 i o = 1.8ma 0.7 v r0 to r4 v os0 i o = C10 m av s2 C0.6 v segment output voltage 1 (1/4 bias) v os1 i o = 10 m a 2/4v s2 C0.6 2/4v s2 +0.6 v seg1 to seg80 v os2 i o = 10 m a 2/4v s2 C0.6 2/4v s2 +0.6 v v os3 i o = +10 m a v ss +0.6 v (v dd = 2.7 to 5.5 v, v bi = 6 to 16 v, ta = C40 to +85?c) lcd driving bias resistance l br 6.3 9 13 k w v 2 to v 3a
? semiconductor ml9090-01,-02 8/38 pedl9090-02 parameter symbol condition min. typ. max. unit applicable pins v os0 i o = C10 m av s2 C0.6 v segment output voltage 2 (1/5 bias) v os1 i o = 10 m a 3/5v s2 C0.6 v seg1 to seg80 v os2 i o = 10 m a 2/5v s2 C0.6 v v os3 i o = +10 m a v ss +0.6 v v oc0 i o = C10 m av s2 C0.3 v common output voltage 2 (1/5 bias) v oc1 i o = 10 m a 4/5v s2 C0.3 v c0m1 to c0m18 v oc2 i o = 10 m a 1/5v s2 C0.3 3/5v s2 +0.6 2/5v s2 +0.6 4/5v s2 +0.3 1/5v s2 +0.3 v v oc3 i o = +10 m a v ss +0.3 v voltage multiplier voltage 1 v db v in 1.83 C0.5 v v s1 voltage multiplier voltage 2 v tr v in 2.46 C1.0 v v s2 supply current 1 i dd1 r = 56k w 2% *1 0.95 ma v dd supply current 2 i dd2 external clock = 740khz *1 0.7 ma v dd (v dd = 2.7 to 5.5 v, v bi = 6 to 16 v, ta = C40 to +85?c) v oc0 i o = C10 m av s2 C0.3 v common output voltage 1 (1/4 bias) v oc1 i o = 10 m a 3/4v s2 C0.3 v c0m1 to c0m18 v oc2 i o = 10 m a 1/4v s2 C0.3 v v oc3 i o = +10 m a v ss +0.3 v 3/4v s2 +0.3 1/4v s2 +0.3 external clock = 740khz *1 external clock = 740khz *1 *1: refer to measuring circuits
? semiconductor ml9090-01,-02 9/38 pedl9090-02 measuring circuits v ss voltage multiplier voltage 1 when voltage doubler is used. test pao seg1 - seg80 com1 - com10 c0 - c4 r0 - r4 open v dd v in v c1 v c2 v s1 v s2 dt v 2 v 3a v 3b cs cp di/o osc2 osc1 open f = 740khz reset v dd v vdb + 4.7 m f 4.7 m f 100 m a open C open open v ss voltage multiplier voltage 2 when voltage tripler is used. test pao seg1 - seg80 com1 - com10 c0 - c4 r0 - r4 open v dd v in v c1 v c2 v s1 v s2 v 2 open dt vdd v 3a v 3b cs cp di/o osc2 osc1 open f = 740khz reset v dd v vdr + 4.7 m f 4.7 m f 4.7 m f 100 m a C + open open v ss supply current 1 test pao seg1 - seg80 com1 - com10 c0 - c4 r0 - r4 open v dd v in v c1 v c2 v s1 cs cp di/o osc2 osc1 reset v dd + 4.7 m f C open open v 2 open dt vdd v 3a v 3b 4.7 m f + v s2 4.7 m f + a iddi v ss supply current 2 test pao seg1 - seg80 com1 - com10 c0 - c4 r0 - r4 open v dd v in v c1 v c2 v s1 cs cp di/o osc2 osc1 open f = 740khz reset v dd + 4.7 m f C open open v 2 open dt vdd v 3a v 3b 4.7 m f + v s2 4.7 m f + a idd2 + + r = 56k w 2% 2.7-5.5v 2.7-5.5v 2.5-8v 2.5-7v 5.5v 6.0v 5.5v 6.0v *1 com11 - com18/ pb0 - pb7 *1 com11 - com18/ pb0 - pb7 *1 com11 - com18/ pb0 - pb7 *1 com11 - com18/ pb0 - pb7 *1: pb0 - pb7 for ml9090-01, and com11 - com18 for ml9090-02
? semiconductor ml9090-01,-02 10/38 pedl9090-02 switching characteristics parameter cp clock cycle time symbol t sys condition unit ns min 1000 max 100 200 200 100 cp "h" pulse width t wh ns 400 cp "l" pulse width t wl ns 400 cs "h" pulse width t wch ns 200 cp clock rise/fall time t r , t f ns cs setup time t csu ns 60 cs hold time t chd ns 290 di/o setup time t dsu ns 100 di/o hold time t dhd ns 15 di/o output delay time t dod cl = 50pf ns di/o output off delay time t doff cl = 50pf ns reset pulse width t wre m s 2 external clock cycle time t ses ns 833 external clock "h" pulse width t weh ns 316 external clock "l" pulse width t wel ns 316 external clock rise/fall time t re , t fe ns (v dd = 2.7 to 5.5 v, v bi = 6 to 16 v, ta = C40 to +85?c)
? semiconductor ml9090-01,-02 11/38 pedl9090-02 clock synchronous serial interface timing diagrams clock synchronous serial interface input timing reset timing cp cs di-o t csu t sys t dhd t wl t wh t r t r t chd t wch v ih4 v il4 v ih3 v ih3 v ih3 v ih4 v ih4 v il4 v il4 v il3 v il3 v ih3 v ih3 v il3 v ih4 v il4 t dsu clock synchronous serial interface input/output timing cp cs di-o t csu t sys t dhd t dod t doff t wl t wh t r t r t chd t wch v ih4 v il4 v ih3 v ih3 8 clock v ih3 v ih4 v ih4 v il4 v oh1 v ol1 v oh1 v ol1 hiz v il4 v il3 v il3 v il3 v ih3 v ih3 v il3 v ih4 v il4 1 clock t dsu reset t wre v il2 v il2 external clock osc1 t ses t wel t re t weh t re v ih1 v ih1 v il1 v il1 v il1
? semiconductor ml9090-01,-02 12/38 pedl9090-02 functional descriptions pin functional descriptions function symbol pin name type no.of pins description cs chip select i 1 chip select signal input pin cpu interface cp clock pulse i 1 shift clock signal input pin. this pin is connected to an internal schmitt circuit di/o data i/o i/o 1 serial data signal i/o pin kreq key request o 1 key request signal output pin oscillation osc1 osc1 i 1 connect external resistors. osc2 osc2 o 1 reset reset i 1 initial settings can be established by pulling the reset input to a "l" level. this pin is connected to an internal schmitt circuit. control signals dt doubler tripler select i1 input pin for selecting the voltage doubler or voltage tripler. test test i 1 test input pin. this pin is connected to the v ss pin. key scan signals c0 to c4 column input i 5 input pins that detect status of key switches r0 to r4 row output o 5 key switch scan signal pins port outputs pa0 port output o 1 port a output pb0 to pb7 port output o 8 port b outputs (for ml9090-01) seg1 to seg80 seg output o 80 outputs for lcd segment drivers lcd driver outputs com1 to com10 com output o 10 outputs for lcd common drivers (for ml9090-01) com1 to com18 com output o 18 outputs for lcd common drivers (for ml9090-02) v dd v dd 1 logic power supply pin v ss v ss 1 gnd pin v in v in 1 voltage multiplier reference voltage power supply pin power supply v c1 , v c2 v c1 , v c2 2 capacitor connection pins for voltage multiplier v s1 v s1 1 voltage doubler output pin v s2 v s2 1 voltage tripler output pin v 2 , v 3a , v 3b v 2 , v 3a , v 3b 3 lcd bias pins
? semiconductor ml9090-01,-02 13/38 pedl9090-02 register list rs r/w register number register symbol register name data bits 3210 76543210 010000 kr key scan register st2 st1 st0 s4 s3 s2 s1 s0 11/00001 dram display data register d7 d6 d5 d4 d3 d2 d1 d0 000010 xad x address register x3x2x1x0 000011 yad y address register y4 y3 y2 y1 y0 000100 pta port register a pa0 000101 ptb port register b pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 001000 fcr1 control register 1 inc wls kt shl dty1 dty0 001001 fcr2 control register 2 t4 t3 t2 t1 disp rs register select bit 1: ram 0: register r/w read/write select bit 1: read 0: write st0 to st2 : scan status s0 to s4 : key scan data d0 to d7 : display data and ram read data x0 to x3 : x address y0 to y4 : y address pa0 : port a data pb0 to pb7 : port b data (ml9090-01 only) inc : address increment 1: x direction, 0: y direction wls : word length select 1: 6 bits, 0: 8 bits kt : key scan cycle select 1: 10 ms, 0: 5 ms dty0, dty1: display duty select (1/8, 1/9, 1/10) (ml9090-01) (1/16, 1/17, 1/18) (ml9090-02) shl : common driver shift direction select bit 1: com10 ? com1, 0 : com1 ? com10 (ml9090-01) 1: com18 ? com1, 0 : com1 ? com18 (ml9090-02) disp : display on/off select 1: display on, 0: display off t1 to t4 : write "0" : don't care
? semiconductor ml9090-01,-02 14/38 pedl9090-02 pin functional descriptions ? cs chip select input pin. an l level selects the chip, and an h level does not select the chip. during the l level, internal registers can be accessed. ? cp clock input pin for serial interface data i/o. an internal schmitt circuit is connected to this pin. data input to the di/o pin is synchronized to the rising edge of the clock. output from the di/ o pin is synchronized to the falling edge of the clock. ? di/o serial interface data i/o pin. this pin is in the output state only during the interval beginning when key scan data read or ram read commands (to be described later) are written (after the rising edge of the 8th cp clock during start byte setup, the cpu changes from output to input and the di/o output interval begins at the cp falling edge) until the cs signal rises. at all other times this pin is in the input state. (when reset, the input state is set.) the relation between data level of this pin and operation is listed below. data level lcd display port key status "h" light on "h" on "l" light off "l" off ? kreq key scan read ready signal output pin. two scan cycles after a key switch is switched on, this pin goes to an h level. when all key switches are off, this pin returns to an l level. begin the key scan read operation after this pin goes to an h level. ? osc1 input pin for rc oscillation. an oscillation circuit is formed by connecting a resistor (r) of 56k w 2% to this pin and the osc2 pin. if an external master oscillation clock is to be input, input the master oscillation clock to this pin. osc1 r r = 56k w 2% osc2 ? osc2 input pin for rc oscillation. an oscillation circuit is formed by connecting a resistor (r) of 56k w 2% to this pin and the osc1 pin. if an external master oscillation clock is to be input, leave this pin unconnected (open).
? semiconductor ml9090-01,-02 15/38 pedl9090-02 ? reset reset signal input pin. the initial state can be set by pulling this pin to an l level. refer to the pin and register states in response to reset input page for the initial states of each register and display. an internal pull-up resistor is connected to this pin. an external capacitor is connected for power- on-reset operation. ? test test signal input pin. this pin is used for testing by oki. connect this pin to v ss . when a different connection is made, proper operation cannot be guaranteed. ? r0 to r4 key switch scan signal output pins. during the scan operation, l level signals are output in the order of r0, r1, ...r4. (refer to the page entitled key scan for further details.) ? c0 to c4 input pins that detect the key switch status. internal pull-up resistors are connected to these pins. assemble a key matrix between these pins and the r0 to r4 pins. ? pa0 general-purpose port a output pin. because this pin can output a current of 15ma, it is best suited as an led driver. if this pin is used as an led driver, insert an external current limiting resistor in series with the led. ? pb0 to pb7 general-purpose port b output pins. each of the pb5 to pb7 pins has the same driving capability as the pa0 pin. these pins are only applicable to the ml9090-01. ? seg1 to seg80 segment signal output pins for lcd driving. leave unused pins unconnected (open). ? com1 to com10 common signal output pins for lcd driving. leave unused pins unconnected (open). ? com1 to com18 common signal output pins for lcd driving. leave unused pins unconnected (open). these pins are applicable to the ml9090-02. ? v dd logic power supply connection pin. ? v ss power supply gnd connection pin.
? semiconductor ml9090-01,-02 16/38 pedl9090-02 ? dt this pin selects the voltage multiplier circuit. if this pin is connected to the v ss pin, the voltage doubler circuit is selected. if this pin is connected to the v dd pin, the voltage tripler circuit is selected. do not change the value of the setting after power is turned on. ? v c1 , v c2 capacitor connection pins for the voltage multiplier. connect a 4.7 m f capacitor between the v c1 and v c2 pins. if an electrolytic capacitor is used, connect the (+) side to pin v c2 . ? v s1 voltage doubler voltage output pin. this pin outputs the doubled voltage that has been input to v in . to increase stability of the power supply, connect a 4.7 m f capacitor between this pin and v ss . when using the doubled voltage, connect this pin and v s2 . ? v s2 voltage multiplier voltage output pin. voltage multiplied by the factor specified by the dt pin setting is output from this pin. when the voltage tripler is used, to increase stability of the power supply, connect a 4.7 m f capacitor between this pin and v ss . when using the voltage doubler, connect this pin and v s1 . ? v in voltage multiplier voltage input pin. the doubled or tripled voltage input to this pin is output from v s2 . ? v 2 , v 3a , v 3b lcd bias pins for segment drivers. these pins are connected to internal bias dividing resistors. when using the ml9090-01 (at 1/4 bias), connect v 2 and v 3a pins, and leave v 3b unconnected (open). when using the ml9090-02 (at 1/5 bias), connect v 3a and v 3b pins, and leave v 2 unconnected (open).
? semiconductor ml9090-01,-02 17/38 pedl9090-02 clock synchronous serial transfer example (write) cs cp transfer start transfer complete di/o register bits rs r/w d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 "1" "1" 12345678910111213141516 1st byte instruction start byte clock synchronous serial continuous data transfer example (write) cs cp transfer start transfer complete di/o 127891015161718232441424748 start byte instruction 1 instruction 2 instruction 5 clock synchronous serial continuous data transfer example (read) cs cp transfer start transfer complete di/o 1289 11 10 15 16 17 18 23 24 41 42 47 48 start byte read data1 read data2 read data5 output state
? semiconductor ml9090-01,-02 18/38 pedl9090-02 register descriptions this ic is constructed from a start byte register and data registers. 1. start byte register d7 d6 d5 d4 d3 d2 d1 d0 "1" "1" rs r/w register number the start byte register selects 8 types of data registers. (1) d7, d6 (fixed at 1) when selecting the start byte register, always write a 1 to bits d7 and d6. if the reset pin is pulled to a l level, these bits are reset to 0. (2) d5 rs (register select bit) 1: ram is selected 0: register is selected this bit specifies whether the selected data register is dram (display data register) or registers different from the display data register. to select dram, write a 1 to this bit. to select registers other than dram, write a 0 to this bit. if the reset pin is pulled to a l level, this bit is reset to 0. (3) d4 r/w (read mode, write mode select bit) 1: read mode is selected 0: write mode is selected this bit specifies either read mode or write mode for the selected data register. to select read mode, write a 1 to this bit. to select write mode, write a 0 to this bit. if the reset pin is pulled to a l level, this bit is reset to 0. (4) d3 to d0 (register number) these bits select the data register. the correspondence between each bit and each register is listed in the table below. if the reset pin is pulled to a l level, these bits are reset to 0. code d3 d2 d1 d0 register name 00000 key scan register 10001 display data register 20010x address register 30011y address register 40100 port a register 50101 port b register 81000 control register 1 91001 control register 2
? semiconductor ml9090-01,-02 19/38 pedl9090-02 2. instructions (data registers) ? key scan register (kr) d7 d6 d5 d4 d3 d2 d1 d0 st2 st1 st0 s4 s3 s2 s1 s0 (1) d7 to d5 st2 to st0 (scan read counter) when reading 25-bit key scan data, these bits indicate the number of times scan data has been read. every time key scan data is read, these bits (st2 to st0) are automatically incremented over the range of 000 to 100. after counting to 100, this key scan data read counter is reset to 000. if the reset pin is pulled to a l level, these bits are reset to 0. (2) d4 to d0 s4 to s0 (key scan read data bits) these bits are read as 25-bit serial data that expresses the key switch status (1 = on, 0 = off). data is divided into 5 groups and read. (for the read order, refer to the description below.) the read count is indicated by bits st2 to st0. s4 to s0 key scan data corresponds to each swn0 of the key matrix shown in figure 1. the relation between the key scan data, key matrix signal and each swn0 of the key matrix is shown below. if the reset pin is pulled to a l level, these bits are reset to 0. st2 0 st1 0 st0 0 s4 sw04 s3 sw03 s2 sw02 s1 sw01 s0 sw00 r0 0 0 1 sw14 sw13 sw12 sw11 sw10 r1 0 1 0 sw24 sw23 sw22 sw21 sw20 r2 0 1 1 sw34 sw33 sw32 sw31 sw30 r3 1 0 0 sw44 sw43 sw42 sw41 sw40 r4
? semiconductor ml9090-01,-02 20/38 pedl9090-02 c0 sw00 c1 sw01 c2 sw02 c3 sw03 c4 r0 sw04 sw10 sw11 sw12 sw13 r1 sw14 sw20 sw21 sw22 sw23 r2 sw24 sw30 sw31 sw32 sw33 r3 sw34 sw40 sw41 sw42 sw43 r4 sw44 ml9090-01, -02 figure 1
? semiconductor ml9090-01,-02 21/38 pedl9090-02 ? display data register (dram) d7 d6 d5 d4 d3 d2 d1 d0 8-bit data 6-bit data the display data register writes and reads display data to and from the liquid crystal display ram. the contents of this register are written to or read from the address set by the x address register and y address register. the bit length of display data can be selected by the wls bit of control register 1. if 6-bit data has been selected, writing to d7 and d6 is invalid, and if read, their values will always be 0. d7 is the msb (d5 in the case of 6-bit data) and d0 is the lsb. the x address and y address should be set immediately before writing or reading display data. however, only one-time settings of x address and y address are required immediately before successive writings or readings. either x address or y address may be set first. even if the reset pin is pulled to a l level, the contents of this register will not change. ? x address register (xad) d7 d6 d5 d4 d3 d2 d1 d0 xad the x address register sets the x address for the display ram. the address setting range is 0 to 9 (00h to 09h) when 8-bit data has been selected by the wls bit (d6 bit) of control register 1, and 0 to 13 (00h to 0dh) when 6-bit data has been selected. proper operation is not guaranteed if values outside this range are set. writing to bits d7 through d4 is invalid, and if read, their values will always be 0. if the reset pin is pulled to a l level, these bits are reset to 0. ? y address register (yad) d7 d6 d5 d4 d3 d2 d1 d0 yad (ml9090-01) yad (ml9090-02) the y address register sets the y address for the display ram. the address setting range for the ml9090-01 is 0 to 7 (00h to 07h) when 1/8 duty has been selected by the dty0 and dty1 bits of control register 1, 0 to 8 (00h to 08h) when 1/9 duty has been selected, and 0 to 9 (00h to 09h) when 1/10 duty has been selected. the address setting range for the ml9090-02 is 0 to 15 (00h to 0fh) when 1/16 duty has been selected by the dty0 and dty1 bits of control register 1, 0 to 16 (00h to 10h) when 1/17 duty has been selected, and 0 to 17 (00h to 11h) when 1/18 duty has been selected. proper operation is not guaranteed if values outside these ranges are set. writing to the d4 bit of the ml9090-01 is valid. therefore, memory (8 80 bits) corresponding to y addresses 10 through 17 can be used as a general-purpose memory. writing to bits d7 through d5 is invalid, and if read, their values will always be 0. when using the ml9090-02, writing to bits d7 through d5 is invalid, and if read, their values will always be 0. if the reset pin is pulled to a l level, these bits are reset to 0.
? semiconductor ml9090-01,-02 22/38 pedl9090-02 ? port register a (pta) d7 d6 d5 d4 d3 d2 d1 d0 pta the port register a sets (to 1) and resets (to 0) general-purpose port a data. the setting of the pta bit (d0 bit) corresponds to the pa0 output pin. if the reset pin is pulled to a l level, this register is reset to 0 and the pa0 pin goes to high impedance. after the reset pin is pulled to a h level, if port data is set in this register, the pa0 pin is released from its high impedance state and outputs the corresponding port data. ? port register b (ptb) d7 d6 d5 d4 d3 d2 d1 d0 ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 the port register sets (to 1) and resets (to 0) general-purpose port b data. the settings of the ptb0 to ptb7 bits (d0 to d7 bits) correspond to the ptb0 to ptb7 output pins. if the reset pin is pulled to a l level, this register is reset to 0 and pins ptb0 through ptb7 go to high impedance. after the reset pin is pulled to a h level, if port data is set in this register, pins ptb0 through ptb7 are released from their high impedance states and output the corresponding port data. ? control register 1 (fcr1) d7 d6 d5 d4 d3 d2 d1 d0 inc wls kt shl dty1 dty0 (1) d7 inc address increment direction 1: x direction address increment 0: y direction address increment this bit sets the address increment direction of the display ram. the display ram address is automatically incremented by 1 every time data is written to the display data register. writing a 1 to this bit sets x address increment, and writing a 0 sets y address increment. for further details regarding address incrementing, refer to the page entitled x, y address counter auto increment, even if the reset pin is pulled to a l level, the value of this bit will not change. (2) d6 wls (word length select) 1: 6-bit word length select 0: 8-bit word length select this bit selects the word length of data to be written to and read from the display ram. if 1 is written to this bit, data will be read from and written to the display ram in 6-bit units. if 0 is written to this bit, data will be read from and written to the display ram in 8-bit units. even if the reset pin is pulled to a l level, the value of this bit will not change.
? semiconductor ml9090-01,-02 23/38 pedl9090-02 (3) d5 kt (key scan time) key scan time select bit 1: 10ms 0: 5ms this bit selects the key scan cycle time. in the case of a 740khz oscillating frequency, writing a 1 to this bit sets the key scan cycle time at 10ms, writing a 0 sets the key scan cycle time at 5ms. even if the reset pin is pulled to a l level, the value of this bit will not change. (4) d4 shl (common driver shift direction select bit) this bit selects the shift direction of common drivers. the relationship between this bit and shift directions are shown below. even if the reset pin is set to "l", this bit remains unchanged. model shl duty shift direction 1/8 com8 com1 ml9090-01 1 1/9 com9 com1 1/10 com10 com1 0 ml9090-02 1 0 ? ? ? 1/8 com1 com8 1/9 com1 com9 1/10 com1 com10 ? ? ? 1/16 com16 com1 1/17 com17 com1 1/18 com18 com1 ? ? ? 1/16 com1 com16 1/17 com1 com17 1/18 com1 com18 ? ? ? (5) d1 to d0 dty (display duty select bit) this bit selects the display duty. the correspondence between each bit and display duty is shown in the chart below. even if the reset pin is pulled to a l level, the values of these bits will not change. model code dty1 dty0 display duty 0001/8 ml9090-01 1011/9 2 1 0 1/10 3 1 1 1/10 0 0 0 1/16 ml9090-02 1 0 1 1/17 2 1 0 1/18 3 1 1 1/18
? semiconductor ml9090-01,-02 24/38 pedl9090-02 ? control register 2 (fcr2) d7 d6 d5 d4 d3 d2 d1 d0 t4 t3 t2 t1 disp (1) d0 disp (display on/off mode bit) 1: display on mode 0: display off mode this bit selects whether the display is on or off. writing a 1 to this bit selects the display on mode. writing a 0 to this bit selects the display off mode. at this time, the com and seg pins will be at the vss level. even if this bit is set to 0, the display ram contents will not change. if the reset pin is pulled to a l level, this register is reset to 0. (2) d2 to d5 t1 to t4 (test mode select bit) these bits are used to test the ic. 0 must be written to these bits.
? semiconductor ml9090-01,-02 25/38 pedl9090-02 display screen and memory address the ml9090 contains an internal bit-mapped display ram (80 18 bits). as shown in figure 2, display data is written to display memory such that the msb of the display data is written to the (xn, yn) memory address and the lsb is written to the (xn+7, yn) address. writing a 1 to the display memory turns on the display of the lcd panel and writing a 0 turns off the display. as shown in figure 3, address allocation is different depending upon whether an 8-bit or 6-bit word length is selected. for an 8-bit word length, addresses are allocated from 0 to 9, and for a 6-bit word length, addresses are allocated from 0 to 13. when 6-bits/word are selected and the x address is 13, the display memory is only 2 bits; 2 bits from the msb of the display data (d5 and d4) are written to memory and the remaining 4 bits (d3 to d0) are invalid. 80 18 dot lcd panel seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg80 com1 com2 com18 80 18 dit display ram x0 x1 x2 x3 x4 x5 x6 x7 x79 y0 y1 y17 10101010 (msb) (lsb) x direction figure 2 correspondence between display screen and memory figure 3 display memory addresses 012 9 0 1 17 (8 bits) 012 13 0 1 17 (6 bits) (2 bits) address allocation for 8 bits/word address allocation for 6 bits/word
? semiconductor ml9090-01,-02 26/38 pedl9090-02 x, y address counter auto increment the display ram of the ml9090-01 and ml9090-02 has an x address counter and a y address counter. both counters have an auto increment function. writing or reading display data will cause either the x or y address counter to be incremented. the inc bit (d7 bit) setting of control register 1 selects either the x address or y address to be incremented. (when x address is selected) (inc = 1) the address count cycle of the x address counter differs depending upon whether the word length is 8 bits or 6 bits. if the word length is 8 bits, x addresses in the range of 0 to 9 are counted. if the word length is 6 bits, x addresses in the range of 0 to 13 are counted. when the x address count value returns from its maximum value (9 in the case of 8-bit word length, 13 in the case of 6-bit word length) to 0, the y address is also automatically incremented. (when y address is selected) (inc = 0) the address count cycle of the y address counter differs depending upon whether the display duty is 1/8, 1/9, 1/10, 1/16, 1/17, or 1/18. if the display duty is 1/8, y addresses in the range of 0 to 7 are counted. if the display duty is 1/9, y addresses in the range of 0 to 8 are counted. if the display duty is 1/10, y addresses in the range of 0 to 9 are counted. if the display duty is 1/16, y addresses in the range of 0 to 15 are counted. if the display duty is 1/17, y addresses in the range of 0 to 16 are counted. if the display duty is 1/18, y addresses in the range of 0 to 17 are counted. when the y address count value returns from its maximum value (7 in the case of 1/8 display duty, 8 in the case of 1/9 display duty, 9 in the case of 1/10 display duty, 15 in the case of 1/16 display duty, 16 in the case of 1/17 display duty, and 17 in the case of 1/18 display duty) to 0, the x address is also automatically incremented. note: if an address outside the count cycle range of the x, y address counter is set, proper operation of the x, y address counter is not guaranteed. 1. x address increment example 2. y address increment example (8-bit word length, 1/18 duty) (8-bit word length, 1/18 duty) 012 9 0 1 17 0 y address x address 0 1 2 17 0 x address y address 190
? semiconductor ml9090-01,-02 27/38 pedl9090-02 output pin, i/o pin and register states when reset is input pin and register states while the reset input is pulled to a l level are listed below. output pin, i/o pin state di/o input state kreq "l" (v ss ) osc2 oscillating state r0 to r4 "l" (v ss ) pba high impedance pb0 to pb7 (for ml9090-01) high impedance seg1 to seg80 "l" (v ss ) com1 to com10 (for ml9090-01) "l" (v ss ) com1 to com18 (for ml9090-02) "l" (v ss ) register state key scan register reset to "0" display data register display data is retained x address register reset to "0" y address register reset to "0" port a register reset to "0" port b register reset to "0" control register 1 no change from value prior to reset input control register 2 display off
? semiconductor ml9090-01,-02 28/38 pedl9090-02 power-on flow chart power turned on normal operation reset is input cs = "l" start byte register setting data register settings cs = "h" cs = "l" start byte register settings data register settings cs = "h" no yes is input of initial screen data complete? cs = "l" start byte register setting data register setting 5 m s external reset or power-on reset chip enable control register 1 setting inc, wls, kt, dty1, dty2 settings according to specifications port register a, port register b, display data register settings according to specifications pa0, pb0 to pb7, d0 to d7 settings control register 1 setting setting the disp bit to "1" starts the initial screen display. cs = "h"
? semiconductor ml9090-01,-02 29/38 pedl9090-02 key scan key scan operation begins after a key switch turns on. key scan operation is halted after all key switches are detected as off. two cycles after key scan operation starts, the kreq signal changes from an l to h level. this signal can be used as a flag. the kreq signal is reset when all key switches have been detected as off and an l level is input to the reset pin. r0 kreq key switch on start scan r1 r2 r3 r4 start reading key data key switch off halt scan note 1: pressing three or more key switches simultaneously may result in incorrect recognition (a switch that was not pressed may be recognized as a switch that was pressed). therefore, if it is necessary to recognize three or more pressed switches, connect a diode in series with each switch. if three or more pressed switches are not to be recognized, data should be ignored if there are three or more 1s in the key data that is read by software. note 2 : because changes in the key status are detected as changes in the column inputs ( c0 to c4 ), changes will not be detected if multiple switches connected to the same column are pressed.
? semiconductor ml9090-01,-02 30/38 pedl9090-02 liquid crystal driving waveform example 1/8 duty (1/4 bias) (ml9090-01) 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 v s2 v 1 v 2 , v 3a , v 3b c0m1 v 4 v ss v s2 v 1 v 2 , v 3a , v 3b c0m2 v 4 v ss v s2 v 1 v 2 , v 3a , v 3b c0m8 v 4 v ss a non-selectable waveform is output from com9 and com10 outputs. 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 v s2 v 1 v 2 , v 3a , v 3b segn v 4 v ss light on light off
? semiconductor ml9090-01,-02 31/38 pedl9090-02 liquid crystal driving waveform example 1/9 duty (1/4 bias) (ml9090-01) 9 1 2 3 4 5 6 7 89 1 2 3 4 5 6 7 8 9 1 v s2 v 1 v 2 , v 3a , v 3b c0m1 v 4 v ss v s2 v 1 v 2 , v 3a , v 3b c0m2 v 4 v ss v s2 v 1 v 2 , v 3a , v 3b c0m9 v 4 v ss a non-selectable waveform is output from the com10 output. 9 1 2 3 4 5 6 7 89 1 2 3 4 5 6 7 8 9 1 v s2 v 1 v 2 , v 3a , v 3b segn v 4 v ss light on light off
? semiconductor ml9090-01,-02 32/38 pedl9090-02 liquid crystal driving waveform example 1/10 duty (1/4 bias) (ml9090-01) 10 1 2 3 4 5 6 7 89 1 2 3 4 5 6 7 8 9 v s2 v 1 v 2 , v 3a , v 3b c0m1 v 4 v ss 10 10 v s2 v 1 v 2 , v 3a , v 3b c0m2 v 4 v ss v s2 v 1 v 2 , v 3a , v 3b c0m10 v 4 v ss 10 1 2 3 4 5 6 7 89 1 2 3 4 5 6 7 8 9 v s2 v 1 v 2 , v 3a , v 3b segn v 4 v ss 10 10 light on light off
? semiconductor ml9090-01,-02 33/38 pedl9090-02 liquid crystal driving waveform example 1/16 duty (1/5 bias) (ml9090-02) 15 1 3 5 7 9 11 13 15 1 3 56 v s2 v 1 v 2 c0m1 v 4 v 3a , v 3b v ss 16 2468 10 12 14 16 13579 11 13 15 2468 10 12 14 16 24 v s2 v 1 v 2 c0m2 v 4 v 3a , v 3b v ss v s2 v 1 v 2 c0m16 v 4 v 3a , v 3b v ss a non-selectable waveform is output from com17 and com18 outputs. 15 1 3 5 7 9 11 13 15 1 3 56 v s2 v 1 v 2 segn v 4 v 3a , v 3b v ss 16 2468 10 12 14 16 13579 11 13 15 2468 10 12 14 16 24 light on light off
? semiconductor ml9090-01,-02 34/38 pedl9090-02 application circuits application example 1 (1/10 duty, voltage doubler) open + + 56k w 1 m f 4.7 m f 4.7 m f ml9090-01 general-purpose ports port or sirial port com1 - com10 seg1 - seg80 pb0 - pb7 co c1 c2 c3 c4 v dd dt pa0 osc1 osc2 test reset r4 r3 r2 r1 r0 v cc v in v c1 v c2 v s1 v s2 v ss v 2 v 3b v 3a cs cp di/o kreq 80 8 dot (graphic) 80 2 dot (arbitrator) 5 5 key matrix temperature compensating and stabilizing circuits lcd panel 80 8 dot (graphic)
? semiconductor ml9090-01,-02 35/38 pedl9090-02 application example 2 (1/18 duty, voltage tripler) + + 56k w 1 m f 4.7 m f 4.7 m f ml9090-02 port or sirial port com1 - com18 seg1 - seg80 co c1 c2 c3 c4 v dd dt pa0 osc1 osc2 test reset r4 r3 r2 r1 r0 v cc v in v c1 v c2 v s1 v s2 v ss v 2 v 3b v 3a cs cp di/o kreq 5 5 key matrix open + 4.7 m f temperature compensating and stabilizing circuits 80 16 dot (graphic) 80 2 dot (arbitrator) lcd panel
? semiconductor ml9090-01,-02 36/38 pedl9090-02 [cautions] ? when the power supply is on or off, the following power supply sequence should be used. at the time of power supply on: logic power supply on ? multiplied reference voltage (v in ) supply on at the time of power supply off: multiplied reference voltage (v in ) supply off ? logic power supply off or both off ? the lines between output pins, and between output pins and other pins (input pins, i/o pins or power supply pins) should not be short circuited.
? semiconductor ml9090-01,-02 37/38 pedl9090-02 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp128-p-1420-0.50-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.19 typ. mirror finish package dimensions
38/38 pedl9090-02 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 2000 oki electric industry co., ltd. printed in japan

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